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Hanging while testing clash-protocols code
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16
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195
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February 14, 2025
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Tricking Haskell into state: how Clash's Signal type works
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0
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81
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February 7, 2025
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Clash Talk slides - FP Syd 27 Nov 2024
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3
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92
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December 20, 2024
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Welcome to Clash Language Community! :wave:
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0
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86
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January 19, 2024
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New Blog Post: Introducing checked-literals: compile-time bounds checking for numeric literals
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0
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15
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April 7, 2026
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The Compiler User Guide has a new home!
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0
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66
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July 30, 2025
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How to obtain the clock period/frequency from the domain?
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3
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113
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November 13, 2024
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Converting `Vec` to `BitVector`
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2
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117
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May 6, 2024
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Clash with LLVM/MLIR circt
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0
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101
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September 27, 2024
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Clash Language Server
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8
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146
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June 13, 2024
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How to write to a blockRam?
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6
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142
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July 2, 2024
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Stateful simulation
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8
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120
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February 2, 2026
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`moore` function in Clash
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1
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77
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October 16, 2024
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Circuit notation for cyclic circuits
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6
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127
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May 19, 2025
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How to dynamically shift a BitVector?
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6
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119
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October 31, 2025
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Using numeric bounds with `Vec` functions, going from `1 <= n => Vec n a` to `Vec (m + 1) a`
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2
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55
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April 4, 2024
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Lsp for shake based project
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1
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65
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November 13, 2025
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Laziness in prod3C
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6
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108
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June 18, 2025
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Generated verilog code is working funny for +>> on Vec
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6
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107
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February 9, 2025
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Using Blackbox to instantiate some HDL
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3
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131
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November 15, 2024
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Verilog conversion: NFDataX for functions
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4
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112
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December 10, 2024
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Very slow simulation of recursive function in Clashi
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1
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55
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January 24, 2025
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`Circuit` currying
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4
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95
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April 25, 2025
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Initializing one word of asyncRam
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4
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86
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November 25, 2025
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deriveAutoReg with superclass constraints
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4
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81
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December 4, 2025
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How to use a BlackBox to specify a predefined type in existing HDL
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2
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101
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December 21, 2024
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Is there an upper limit to the number of items in tuple?
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6
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66
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May 10, 2025
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Verilog and Vivado: 'x' (unknown logic value) is not supported by IP Packager
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1
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122
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June 4, 2024
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We’d love your feedback on using Clash
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3
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85
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February 25, 2026
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Is `clash` able to generate module with constant parameters to be determined in vivado top entity?
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3
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74
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August 7, 2025
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AutoReg - Uses beyond Maybe
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1
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102
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August 8, 2024
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Re-creating a stalling property test
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3
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71
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November 18, 2025
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Integrating Clash kernels with Vitis
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1
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100
|
June 10, 2024
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How to avoid flattening of fields in Record?
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3
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63
|
May 14, 2025
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Have `forall n . KnownNat n` but gives type mismatch error for a vector on successive recursion
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2
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72
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October 6, 2024
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Generate HDL from a file not part of a cabal library
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2
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68
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April 8, 2024
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Test bench rapidly consuming all of my memory
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2
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63
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October 17, 2025
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VSCode integration with Clash - Failed to parse result of calling cabal; also a build error on Clash Cabal package
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6
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41
|
October 12, 2025
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Best way to get pretty waveforms? / issues with dumpVCD
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3
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54
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February 2, 2026
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Type variable dom0 is ambiguous when using DomainPeriod
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2
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62
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June 12, 2024
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How to generate testbench for a combinational circuit?
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1
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74
|
November 8, 2024
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Unexpected Behavior with CLog and SNat?
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2
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60
|
September 25, 2024
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Floating points?
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2
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57
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October 28, 2025
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Infinite recursion error in tutorial code
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2
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56
|
October 10, 2025
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How to handle undefined
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4
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35
|
March 17, 2026
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Simulation just hangs
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6
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29
|
April 9, 2026
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Register signal from applicative functor is not calculated
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2
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42
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April 24, 2025
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sampleN holds reset for one cycle
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1
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51
|
November 13, 2024
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Blinking light n times
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3
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33
|
March 25, 2026
|
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Unclear unsafeFromMaybe
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3
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29
|
March 26, 2026
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