Verilog and Vivado: 'x' (unknown logic value) is not supported by IP Packager

Clash Help
1

When I convert my Clash design to Verilog and then try to add it to a block design in Vivado, I get the following error: ‘x’ (unknown logic value) is not supported by IP Packager". Is there any way to fix this?

2

You can use the -fclash-force-undefined flag to force all undefined values to either 0 or 1.

https://clash-lang.readthedocs.io/en/latest/developing-hardware/flags.html
e.g.:

cabal run clash -- <MODULE> --verilog -fclash-force-undefined=0
1 Like