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Welcome to Clash Language Community! :wave:
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0
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61
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January 19, 2024
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About the Clash Help category
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0
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5
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January 19, 2024
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Laziness in prod3C
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6
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67
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June 18, 2025
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Circuit notation for cyclic circuits
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6
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78
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May 19, 2025
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How to avoid flattening of fields in Record?
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3
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22
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May 14, 2025
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Is there an upper limit to the number of items in tuple?
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6
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27
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May 10, 2025
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`Circuit` currying
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4
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67
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April 25, 2025
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Register signal from applicative functor is not calculated
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2
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25
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April 24, 2025
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Hanging while testing clash-protocols code
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16
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129
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February 14, 2025
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Generated verilog code is working funny for +>> on Vec
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6
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67
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February 9, 2025
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Very slow simulation of recursive function in Clashi
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1
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35
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January 24, 2025
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How to use a BlackBox to specify a predefined type in existing HDL
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2
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69
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December 21, 2024
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Clash Talk slides - FP Syd 27 Nov 2024
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3
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59
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December 20, 2024
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Verilog conversion: NFDataX for functions
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4
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79
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December 10, 2024
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Using Blackbox to instantiate some HDL
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3
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62
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November 15, 2024
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How to obtain the clock period/frequency from the domain?
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3
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50
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November 13, 2024
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sampleN holds reset for one cycle
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1
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30
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November 13, 2024
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How to generate testbench for a combinational circuit?
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1
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53
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November 8, 2024
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`moore` function in Clash
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1
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51
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October 16, 2024
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Have `forall n . KnownNat n` but gives type mismatch error for a vector on successive recursion
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2
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63
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October 6, 2024
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Clash with LLVM/MLIR circt
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0
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80
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September 27, 2024
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Unexpected Behavior with CLog and SNat?
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2
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48
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September 25, 2024
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AutoReg - Uses beyond Maybe
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1
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86
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August 8, 2024
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How to write to a blockRam?
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6
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96
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July 2, 2024
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Clash Language Server
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8
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106
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June 13, 2024
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Type variable dom0 is ambiguous when using DomainPeriod
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2
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55
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June 12, 2024
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Integrating Clash kernels with Vitis
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1
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64
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June 10, 2024
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Verilog and Vivado: 'x' (unknown logic value) is not supported by IP Packager
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1
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106
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June 4, 2024
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Converting `Vec` to `BitVector`
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2
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105
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May 6, 2024
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Generate HDL from a file not part of a cabal library
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2
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57
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April 8, 2024
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