I’m looking to implement a register file with a zero register. In previous Verilog projects, I found the most performant way to do this was to make an asynchronous RAM initialized to have 0 in the zero-register position and gate the write-enable based on the address being nonzero.
In Clash it seems like the asyncRam primitive doesn’t have an initialization option. Is there a way to implement this behavior? The options that leap to mind are either another primitive that I haven’t found yet or some way of introducing a register write during the reset phase, but I don’t know my way around the documentation well enough yet to be able to know if such things are possible.