Is `clash` able to generate module with constant parameters to be determined in vivado top entity?

Clash Help
1

Hi, I’m new to clash and have some maybe stupid questions:

Is clash able to generate verilog that contains modules with constant parameters that is to be determined in vivado top module?

Thanks.

2

Hi astrojhgu, welcome!

If I understand your question correctly, the answer would be: no, that is not possible. Varying parameters in your design would be done through type polymorphism in your Clash design, but the top entity of your design needs to be monomorphic. This says that the actual value for the parameters is computed at compile-time, when generating HDL. So the generated HDL has no parameters to be changed anymore.

So while it is perfectly possible to use this function in your Clash design:

f :: KnownNat n => Vec n Int -> Int
f = sum

this is not suitable as a top entity, because n is left polymorphic. You could use your f in a top entity like:

topEntity :: Vec 5 Int -> Int
topEntity = f

fixing n to 5. Other uses of f can of course use other n’s. It’s just the top entity that needs to be monomorphic.

3

Thanks DigitalBrains.

I understand.

The problem that I’m facing is that I’m coding my board rfsoc board with vivado. The data acquired by the ADC need to be transmitted through the 100G ethernet port. Both end of the data processing chain requires vivado IP cores.

This means that the top module has to be managed by vivado, and I can only do with clash is to write some small modules. And some modules required to be parameterized. That is the reason why I need this feature that I described in my question.

4

Note that you can easily generate multiple Clash logical entities in one go. So if you have some parameterized function f that you want to use for n= 3,4,5, you can do the following:

module Top where

import Clash.Prelude

type T n = Vec n Int -> Int

f :: KnownNat n => T n
f = sum

f3 :: T 3
f3 = f
{-# ANN f3 (defSyn "f3") #-}
{-# OPAQUE f3 #-}

f4 :: T 4
f4 = f
{-# ANN f4 (defSyn "f4") #-}
{-# OPAQUE f4 #-}

f5 :: T 5
f5 = f
{-# ANN f5 (defSyn "f5") #-}
{-# OPAQUE f5 #-}

(see Clash.Annotations.TopEntity)

If you now invoke stack run clash -- --verilog Top, you’ll get:

verilog/Top.f3
verilog/Top.f4
verilog/Top.f5

which you can plug into your Vivado top entity.

These logical entities can reference each other as well, but they can not be mutually recursive.

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