|
Very slow simulation of recursive function in Clashi
|
|
1
|
72
|
January 24, 2025
|
|
How to use a BlackBox to specify a predefined type in existing HDL
|
|
2
|
109
|
December 21, 2024
|
|
Clash Talk slides - FP Syd 27 Nov 2024
|
|
3
|
114
|
December 20, 2024
|
|
Verilog conversion: NFDataX for functions
|
|
4
|
180
|
December 10, 2024
|
|
Using Blackbox to instantiate some HDL
|
|
3
|
176
|
November 15, 2024
|
|
How to obtain the clock period/frequency from the domain?
|
|
3
|
185
|
November 13, 2024
|
|
sampleN holds reset for one cycle
|
|
1
|
65
|
November 13, 2024
|
|
How to generate testbench for a combinational circuit?
|
|
1
|
104
|
November 8, 2024
|
|
`moore` function in Clash
|
|
1
|
98
|
October 16, 2024
|
|
Have `forall n . KnownNat n` but gives type mismatch error for a vector on successive recursion
|
|
2
|
101
|
October 6, 2024
|
|
Clash with LLVM/MLIR circt
|
|
0
|
128
|
September 27, 2024
|
|
Unexpected Behavior with CLog and SNat?
|
|
2
|
73
|
September 25, 2024
|
|
AutoReg - Uses beyond Maybe
|
|
1
|
111
|
August 8, 2024
|
|
How to write to a blockRam?
|
|
6
|
184
|
July 2, 2024
|
|
Clash Language Server
|
|
8
|
256
|
June 13, 2024
|
|
Type variable dom0 is ambiguous when using DomainPeriod
|
|
2
|
92
|
June 12, 2024
|
|
Integrating Clash kernels with Vitis
|
|
1
|
139
|
June 10, 2024
|
|
Verilog and Vivado: 'x' (unknown logic value) is not supported by IP Packager
|
|
1
|
179
|
June 4, 2024
|
|
Converting `Vec` to `BitVector`
|
|
2
|
137
|
May 6, 2024
|
|
Generate HDL from a file not part of a cabal library
|
|
2
|
102
|
April 8, 2024
|
|
Using numeric bounds with `Vec` functions, going from `1 <= n => Vec n a` to `Vec (m + 1) a`
|
|
2
|
71
|
April 4, 2024
|