Clash Help
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How to generate testbench for a combinational circuit?
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1 | 72 | November 8, 2024 |
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`moore` function in Clash
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1 | 75 | October 16, 2024 |
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Have `forall n . KnownNat n` but gives type mismatch error for a vector on successive recursion
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2 | 72 | October 6, 2024 |
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Clash with LLVM/MLIR circt
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0 | 101 | September 27, 2024 |
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Unexpected Behavior with CLog and SNat?
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2 | 58 | September 25, 2024 |
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AutoReg - Uses beyond Maybe
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1 | 101 | August 8, 2024 |
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How to write to a blockRam?
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6 | 140 | July 2, 2024 |
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Clash Language Server
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8 | 139 | June 13, 2024 |
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Type variable dom0 is ambiguous when using DomainPeriod
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2 | 62 | June 12, 2024 |
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Integrating Clash kernels with Vitis
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1 | 96 | June 10, 2024 |
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Verilog and Vivado: 'x' (unknown logic value) is not supported by IP Packager
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1 | 120 | June 4, 2024 |
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Converting `Vec` to `BitVector`
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2 | 114 | May 6, 2024 |
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Generate HDL from a file not part of a cabal library
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2 | 67 | April 8, 2024 |
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Using numeric bounds with `Vec` functions, going from `1 <= n => Vec n a` to `Vec (m + 1) a`
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2 | 54 | April 4, 2024 |