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How to use a BlackBox to specify a predefined type in existing HDL
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2
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104
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December 21, 2024
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Clash Talk slides - FP Syd 27 Nov 2024
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3
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111
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December 20, 2024
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Verilog conversion: NFDataX for functions
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4
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154
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December 10, 2024
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Using Blackbox to instantiate some HDL
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3
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159
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November 15, 2024
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How to obtain the clock period/frequency from the domain?
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3
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147
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November 13, 2024
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sampleN holds reset for one cycle
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1
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56
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November 13, 2024
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How to generate testbench for a combinational circuit?
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1
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99
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November 8, 2024
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`moore` function in Clash
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1
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87
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October 16, 2024
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Have `forall n . KnownNat n` but gives type mismatch error for a vector on successive recursion
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2
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87
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October 6, 2024
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Clash with LLVM/MLIR circt
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0
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117
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September 27, 2024
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Unexpected Behavior with CLog and SNat?
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2
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69
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September 25, 2024
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AutoReg - Uses beyond Maybe
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1
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106
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August 8, 2024
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How to write to a blockRam?
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6
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156
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July 2, 2024
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Clash Language Server
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8
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233
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June 13, 2024
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Type variable dom0 is ambiguous when using DomainPeriod
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2
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83
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June 12, 2024
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Integrating Clash kernels with Vitis
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1
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122
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June 10, 2024
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Verilog and Vivado: 'x' (unknown logic value) is not supported by IP Packager
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1
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141
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June 4, 2024
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Converting `Vec` to `BitVector`
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2
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131
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May 6, 2024
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Generate HDL from a file not part of a cabal library
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2
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90
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April 8, 2024
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Using numeric bounds with `Vec` functions, going from `1 <= n => Vec n a` to `Vec (m + 1) a`
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2
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65
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April 4, 2024
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