| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| How to generate testbench for a combinational circuit? |
|
1 | 70 | November 8, 2024 |
| `moore` function in Clash |
|
1 | 74 | October 16, 2024 |
| Have `forall n . KnownNat n` but gives type mismatch error for a vector on successive recursion |
|
2 | 72 | October 6, 2024 |
| Clash with LLVM/MLIR circt |
|
0 | 100 | September 27, 2024 |
| Unexpected Behavior with CLog and SNat? |
|
2 | 58 | September 25, 2024 |
| AutoReg - Uses beyond Maybe |
|
1 | 101 | August 8, 2024 |
| How to write to a blockRam? |
|
6 | 137 | July 2, 2024 |
| Clash Language Server |
|
8 | 127 | June 13, 2024 |
| Type variable dom0 is ambiguous when using DomainPeriod |
|
2 | 62 | June 12, 2024 |
| Integrating Clash kernels with Vitis |
|
1 | 79 | June 10, 2024 |
| Verilog and Vivado: 'x' (unknown logic value) is not supported by IP Packager |
|
1 | 119 | June 4, 2024 |
| Converting `Vec` to `BitVector` |
|
2 | 114 | May 6, 2024 |
| Generate HDL from a file not part of a cabal library |
|
2 | 66 | April 8, 2024 |
| Using numeric bounds with `Vec` functions, going from `1 <= n => Vec n a` to `Vec (m + 1) a` |
|
2 | 54 | April 4, 2024 |