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Register signal from applicative functor is not calculated
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2
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42
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April 24, 2025
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Hanging while testing clash-protocols code
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16
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196
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February 14, 2025
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Generated verilog code is working funny for +>> on Vec
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6
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107
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February 9, 2025
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Tricking Haskell into state: how Clash's Signal type works
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0
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84
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February 7, 2025
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Very slow simulation of recursive function in Clashi
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1
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55
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January 24, 2025
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How to use a BlackBox to specify a predefined type in existing HDL
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2
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104
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December 21, 2024
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Clash Talk slides - FP Syd 27 Nov 2024
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3
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92
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December 20, 2024
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Verilog conversion: NFDataX for functions
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4
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118
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December 10, 2024
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Using Blackbox to instantiate some HDL
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3
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137
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November 15, 2024
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How to obtain the clock period/frequency from the domain?
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3
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113
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November 13, 2024
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sampleN holds reset for one cycle
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1
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51
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November 13, 2024
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How to generate testbench for a combinational circuit?
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1
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74
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November 8, 2024
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`moore` function in Clash
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1
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81
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October 16, 2024
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Have `forall n . KnownNat n` but gives type mismatch error for a vector on successive recursion
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2
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72
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October 6, 2024
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Clash with LLVM/MLIR circt
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0
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101
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September 27, 2024
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Unexpected Behavior with CLog and SNat?
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2
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60
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September 25, 2024
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AutoReg - Uses beyond Maybe
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1
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102
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August 8, 2024
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How to write to a blockRam?
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6
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146
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July 2, 2024
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Clash Language Server
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8
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147
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June 13, 2024
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Type variable dom0 is ambiguous when using DomainPeriod
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2
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62
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June 12, 2024
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Integrating Clash kernels with Vitis
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1
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101
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June 10, 2024
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Verilog and Vivado: 'x' (unknown logic value) is not supported by IP Packager
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1
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124
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June 4, 2024
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Converting `Vec` to `BitVector`
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2
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117
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May 6, 2024
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Generate HDL from a file not part of a cabal library
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2
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68
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April 8, 2024
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Using numeric bounds with `Vec` functions, going from `1 <= n => Vec n a` to `Vec (m + 1) a`
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2
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55
|
April 4, 2024
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