# Tricking Haskell into state: how Clash's Signal type works

**URL:** https://clash-lang.discourse.group/t/tricking-haskell-into-state-how-clashs-signal-type-works/69
**Category:** Blogs/News
**Tags:** clash-website
**Created:** [February 7, 2025, 10:06am UTC](https://clash-lang.discourse.group/t/tricking-haskell-into-state-how-clashs-signal-type-works/69 "2025-02-07T10:06:10Z")
**Posts on this page:** 1
**Page:** 1

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### Author: ![cuddlefishie](https://yyz2.discourse-cdn.com/free1/user_avatar/clash-lang.discourse.group/cuddlefishie/32/4_2.png) [@cuddlefishie](https://clash-lang.discourse.group/u/cuddlefishie)
#### Post date: [February 7, 2025, 10:06am UTC](https://clash-lang.discourse.group/t/tricking-haskell-into-state-how-clashs-signal-type-works/69/1 "2025-02-07T10:06:10Z")

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Curious how Clash models signals for FPGA and ASIC in Haskell? This short post/tutorial explains this, with an interactive diagram for visualizing clock domain crossing 🤯

> **[Tricking Haskell into state: how Clash's Signal type works](https://clash-lang.org/blog/0007-signals/)**
>
> I recently came across a question on /r/haskell, where /u/netj\_nsh asked whether Clash supports asynchronous circuit designs. They went on to ask whether designing with multiple, synchronous clock domains is possible. While the (very) short answers...