# Initializing one word of asyncRam

**URL:** <https://clash-lang.discourse.group/t/initializing-one-word-of-asyncram/94>\
**Category:** Clash Help\
**Created:** [October 12, 2025, 9:06pm UTC](https://clash-lang.discourse.group/t/initializing-one-word-of-asyncram/94 "2025-10-12T21:06:42Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![bry](https://yyz2.discourse-cdn.com/free1/user_avatar/clash-lang.discourse.group/bry/32/60_2.png) [@bry](https://clash-lang.discourse.group/u/bry)\
**Post date:** [October 12, 2025, 9:06pm UTC](https://clash-lang.discourse.group/t/initializing-one-word-of-asyncram/94/1 "2025-10-12T21:06:42Z")

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I’m looking to implement a register file with a zero register. In previous Verilog projects, I found the most performant way to do this was to make an asynchronous RAM initialized to have 0 in the zero-register position and gate the write-enable based on the address being nonzero.

In Clash it seems like the `asyncRam` primitive doesn’t have an initialization option. Is there a way to implement this behavior? The options that leap to mind are either another primitive that I haven’t found yet or some way of introducing a register write during the reset phase, but I don’t know my way around the documentation well enough yet to be able to know if such things are possible.

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**Author:** ![martijnbastiaan](https://yyz2.discourse-cdn.com/free1/user_avatar/clash-lang.discourse.group/martijnbastiaan/32/11_2.png) [@martijnbastiaan](https://clash-lang.discourse.group/u/martijnbastiaan)\
**Post date:** [November 15, 2025, 9:15am UTC](https://clash-lang.discourse.group/t/initializing-one-word-of-asyncram/94/2 "2025-11-15T09:15:15Z")

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I also don’t see a way to do that right away, but it seems like a good feature to have. Could you open an issue on the issue tracker?

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**Author:** ![leonschoorl](https://yyz2.discourse-cdn.com/free1/user_avatar/clash-lang.discourse.group/leonschoorl/32/13_2.png) [@leonschoorl](https://clash-lang.discourse.group/u/leonschoorl)\
**Post date:** [November 18, 2025, 2:21pm UTC](https://clash-lang.discourse.group/t/initializing-one-word-of-asyncram/94/3 "2025-11-18T14:21:18Z")

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The tricky thing would probably be coming up with a good API for such a feature.

I’ve seen people write small wrappers these things, something like:

```haskell
regFile :: _ => SNat n -> Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a
regFile size rd wr = res
 where
  res = mux (rd .==. 0) (pure 0) (asyncRam size rd wr')
  wr' = fmap ignoreWrite0 wr
  ignoreWrite0 (Just (0,_)) = Nothing
  ignoreWrite0 x = x

```

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<div class="post-metadata">

**Author:** ![bry](https://yyz2.discourse-cdn.com/free1/user_avatar/clash-lang.discourse.group/bry/32/60_2.png) [@bry](https://clash-lang.discourse.group/u/bry)\
**Post date:** [November 25, 2025, 5:48pm UTC](https://clash-lang.discourse.group/t/initializing-one-word-of-asyncram/94/4 "2025-11-25T17:48:59Z")

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I don’t know if the Clash side is smart enough to optimize that properly - my design isn’t far enough along to start testing in hardware yet - but in a previous plain-Verilog implementation yosys+nextpnr generated substantially faster bitstreams when using an initialized RAM primitive rather than a mux. I have something like that in my current implementation but I suspect it will be slow.

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**Author:** ![DigitalBrains](https://yyz2.discourse-cdn.com/free1/user_avatar/clash-lang.discourse.group/digitalbrains/32/28_2.png) [@DigitalBrains](https://clash-lang.discourse.group/u/DigitalBrains)\
**Post date:** [November 25, 2025, 7:51pm UTC](https://clash-lang.discourse.group/t/initializing-one-word-of-asyncram/94/5 "2025-11-25T19:51:14Z")

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> [@bry](#):
>
> I don’t know if the Clash side is smart enough to optimize that properly

Clash will not optimise this, no. Thanks for the issue report!