# Latest **URL:** https://clash-lang.discourse.group/latest.md?page=1 [Latest](https://clash-lang.discourse.group/latest.md) · [Categories](https://clash-lang.discourse.group/categories.md) · [Tags](https://clash-lang.discourse.group/tags.md) **Page:** 2 --- ## [Is there an upper limit to the number of items in tuple?](https://clash-lang.discourse.group/t/is-there-an-upper-limit-to-the-number-of-items-in-tuple/78)
**Author:** [@Bipinoli](https://clash-lang.discourse.group/u/Bipinoli)\ **Replies:** 6\ **Last updated:** [May 10, 2025, 10:47am UTC](https://clash-lang.discourse.group/t/is-there-an-upper-limit-to-the-number-of-items-in-tuple/78 "2025-05-10T10:47:24Z")
Clash fails to compile when using tuples larger than size 12. This seems somewhat arbitrary. My guess is that Clash defines bundle and unbundle functions only for tuples up to a certain size—possibly 12—and lacks suppor… --- ## [\`Circuit\` currying](https://clash-lang.discourse.group/t/circuit-currying/74)
**Author:** [@rslawson](https://clash-lang.discourse.group/u/rslawson)\ **Replies:** 4\ **Last updated:** [April 25, 2025, 11:37pm UTC](https://clash-lang.discourse.group/t/circuit-currying/74 "2025-04-25T23:37:51Z")
I don’t have a particular use case for it now, but I mistakenly thought I did a moment ago. Anywho, I’m curious - is there a way to write some function that allows for something like curryCircuit2 :: forall a b c. F… --- ## [Register signal from applicative functor is not calculated](https://clash-lang.discourse.group/t/register-signal-from-applicative-functor-is-not-calculated/75)
**Author:** [@Bipinoli](https://clash-lang.discourse.group/u/Bipinoli)\ **Replies:** 2\ **Last updated:** [April 24, 2025, 11:39am UTC](https://clash-lang.discourse.group/t/register-signal-from-applicative-functor-is-not-calculated/75 "2025-04-24T11:39:50Z")
Hi, for the circuit: module Debug where import Clash.Prelude type Input = (Bool, Bool) func :: HiddenClockResetEnable dom =\> Signal dom Input -\> Signal dom Int func input = cursor where cursor = register… --- ## [Hanging while testing clash-protocols code](https://clash-lang.discourse.group/t/hanging-while-testing-clash-protocols-code/70)
**Author:** [@harris-chris](https://clash-lang.discourse.group/u/harris-chris)\ **Replies:** 16\ **Last updated:** [February 14, 2025, 3:43pm UTC](https://clash-lang.discourse.group/t/hanging-while-testing-clash-protocols-code/70 "2025-02-14T15:43:23Z")
Hello all, I was wondering if I could ask for some help on the following issue. I have a trivial topEntity function, using clash-protocols, that plugs into an Axi 4 Stream: roundTripTopEntity :: Clock System … --- ## [Generated verilog code is working funny for +\>\> on Vec](https://clash-lang.discourse.group/t/generated-verilog-code-is-working-funny-for-on-vec/67)
**Author:** [@Bipinoli](https://clash-lang.discourse.group/u/Bipinoli)\ **Replies:** 6\ **Last updated:** [February 9, 2025, 7:05pm UTC](https://clash-lang.discourse.group/t/generated-verilog-code-is-working-funny-for-on-vec/67 "2025-02-09T19:05:14Z")
Hi, I ran into a weird case while trying to create a FIFO queue. Simulation in Haskell works correctly, but when testing the generated Verilog code with testbench I get the nonsensical outputs. I have tried to isolate on… --- ## [Tricking Haskell into state: how Clash's Signal type works](https://clash-lang.discourse.group/t/tricking-haskell-into-state-how-clashs-signal-type-works/69)
**Author:** [@cuddlefishie](https://clash-lang.discourse.group/u/cuddlefishie)\ **Replies:** 0\ **Last updated:** [February 7, 2025, 10:06am UTC](https://clash-lang.discourse.group/t/tricking-haskell-into-state-how-clashs-signal-type-works/69 "2025-02-07T10:06:10Z")
Curious how Clash models signals for FPGA and ASIC in Haskell? This short post/tutorial explains this, with an interactive diagram for visualizing clock domain crossing :exploding\_head: --- ## [Very slow simulation of recursive function in Clashi](https://clash-lang.discourse.group/t/very-slow-simulation-of-recursive-function-in-clashi/63)
**Author:** [@Bipinoli](https://clash-lang.discourse.group/u/Bipinoli)\ **Replies:** 1\ **Last updated:** [January 24, 2025, 11:52am UTC](https://clash-lang.discourse.group/t/very-slow-simulation-of-recursive-function-in-clashi/63 "2025-01-24T11:52:28Z")
I get a very slow simulation of values in Clashi for the following function. I don’t see anything wrong with the generated verilog code though. I guess that the simulator might be stuck in some recursive calls. Any ide… --- ## [How to use a BlackBox to specify a predefined type in existing HDL](https://clash-lang.discourse.group/t/how-to-use-a-blackbox-to-specify-a-predefined-type-in-existing-hdl/60)
**Author:** [@tich](https://clash-lang.discourse.group/u/tich)\ **Replies:** 2\ **Last updated:** [December 21, 2024, 9:11pm UTC](https://clash-lang.discourse.group/t/how-to-use-a-blackbox-to-specify-a-predefined-type-in-existing-hdl/60 "2024-12-21T21:11:54Z")
I would like Synthesize topEntity to generate the following code Note packet\_control\_t is predefined type: library nuand; use nuand.fifo\_readwrite\_p.all; entity gnodeb\_top is port ( tx\_clock : … --- ## [Clash Talk slides - FP Syd 27 Nov 2024](https://clash-lang.discourse.group/t/clash-talk-slides-fp-syd-27-nov-2024/55)
**Author:** [@Axman6](https://clash-lang.discourse.group/u/Axman6)\ **Replies:** 3\ **Last updated:** [December 20, 2024, 8:34am UTC](https://clash-lang.discourse.group/t/clash-talk-slides-fp-syd-27-nov-2024/55 "2024-12-20T08:34:47Z")
Hello all, I gave a talk on Clash at the Sydney Functional Programming Group (FP Syd) last months, and I’ve uploaded the slides as some people in the slack channel were interested. This talk was originally written for m… --- ## [Verilog conversion: NFDataX for functions](https://clash-lang.discourse.group/t/verilog-conversion-nfdatax-for-functions/54)
**Author:** [@Julin](https://clash-lang.discourse.group/u/Julin)\ **Replies:** 4\ **Last updated:** [December 10, 2024, 12:12am UTC](https://clash-lang.discourse.group/t/verilog-conversion-nfdatax-for-functions/54 "2024-12-10T00:12:06Z")
I was trying this program: module FinFnsBool where import Clash.Prelude tf :: (Bool -\> Bool) -\> Bool -\> (Bool -\> Bool, Bool) tf f b = (not . f, f b) tfun :: SystemClockResetEnable =\> Signal System Bool -\> … --- ## [Using Blackbox to instantiate some HDL](https://clash-lang.discourse.group/t/using-blackbox-to-instantiate-some-hdl/52)
**Author:** [@zebrasecret](https://clash-lang.discourse.group/u/zebrasecret)\ **Replies:** 3\ **Last updated:** [November 15, 2024, 9:49am UTC](https://clash-lang.discourse.group/t/using-blackbox-to-instantiate-some-hdl/52 "2024-11-15T09:49:03Z")
I’m trying to use BlackBox, but I’m having a hard time getting things to work in the way I want. What I wanna do is have the Clash generated Verilog instantiate into my BlackBox’d Verilog module. First, my verilog fi… --- ## [How to obtain the clock period/frequency from the domain?](https://clash-lang.discourse.group/t/how-to-obtain-the-clock-period-frequency-from-the-domain/50)
**Author:** [@Bipinoli](https://clash-lang.discourse.group/u/Bipinoli)\ **Replies:** 3\ **Last updated:** [November 13, 2024, 4:05pm UTC](https://clash-lang.discourse.group/t/how-to-obtain-the-clock-period-frequency-from-the-domain/50 "2024-11-13T16:05:33Z")
Hi, can the clock period/frequency be obtained from the domain? I am creating a slower clock with a desired frequency by counting the difference from the system clock, as shown below. My understanding is that the domai… --- ## [sampleN holds reset for one cycle](https://clash-lang.discourse.group/t/samplen-holds-reset-for-one-cycle/51)
**Author:** [@Bipinoli](https://clash-lang.discourse.group/u/Bipinoli)\ **Replies:** 1\ **Last updated:** [November 13, 2024, 12:27pm UTC](https://clash-lang.discourse.group/t/samplen-holds-reset-for-one-cycle/51 "2024-11-13T12:27:47Z")
Hi, can anyone help me understand why register along with fromList works the way it does in Clash?Example from the Hakage Clash Prelude: sampleN @System 5 (register 8 (fromList \[1,1,2,3,4\])) \[8,8,1,2,3\] I would have e… --- ## [How to generate testbench for a combinational circuit?](https://clash-lang.discourse.group/t/how-to-generate-testbench-for-a-combinational-circuit/47)
**Author:** [@Bipinoli](https://clash-lang.discourse.group/u/Bipinoli)\ **Replies:** 1\ **Last updated:** [November 8, 2024, 3:06pm UTC](https://clash-lang.discourse.group/t/how-to-generate-testbench-for-a-combinational-circuit/47 "2024-11-08T15:06:59Z")
Hi, Is there an example showing how to generate a verilog/vhdl testbench for a combinational circuit? Also, I assign undefined value to model verilog’s (z, x) state. How can I match for that for an expected output in t… --- ## [\`moore\` function in Clash](https://clash-lang.discourse.group/t/moore-function-in-clash/48)
**Author:** [@Bipinoli](https://clash-lang.discourse.group/u/Bipinoli)\ **Replies:** 1\ **Last updated:** [October 16, 2024, 11:47am UTC](https://clash-lang.discourse.group/t/moore-function-in-clash/48 "2024-10-16T11:47:12Z")
I am confused by how moore function has been defined in Clash. Shouldn’t moore machines depend only on it’s current state? Something like: mooreMachine :: (HiddenClockResetEnable dom, NFDataX s) =\> (s -\> s) -\> s -\> Sig… --- ## [Have \`forall n . KnownNat n\` but gives type mismatch error for a vector on successive recursion](https://clash-lang.discourse.group/t/have-forall-n-knownnat-n-but-gives-type-mismatch-error-for-a-vector-on-successive-recursion/46)
**Author:** [@Bipinoli](https://clash-lang.discourse.group/u/Bipinoli)\ **Replies:** 2\ **Last updated:** [October 6, 2024, 3:54pm UTC](https://clash-lang.discourse.group/t/have-forall-n-knownnat-n-but-gives-type-mismatch-error-for-a-vector-on-successive-recursion/46 "2024-10-06T15:54:34Z")
Hi, I am trying to write a simple 8-bit ripple carry adder in Clash as shown in the code below which doesn’t work atm. As per my understanding, forall n. KnownNat n puts the type-constraints saying that n is known at c… --- ## [Clash with LLVM/MLIR circt](https://clash-lang.discourse.group/t/clash-with-llvm-mlir-circt/45)
**Author:** [@Bipinoli](https://clash-lang.discourse.group/u/Bipinoli)\ **Replies:** 0\ **Last updated:** [September 27, 2024, 2:36pm UTC](https://clash-lang.discourse.group/t/clash-with-llvm-mlir-circt/45 "2024-09-27T14:36:45Z")
Hi, Clash community, I have been exploring Clash for my university thesis. I noticed that the open-source world is converging towards MLIR circt as a common IR layer. Judging by the new research in that area and the in… --- ## [Unexpected Behavior with CLog and SNat?](https://clash-lang.discourse.group/t/unexpected-behavior-with-clog-and-snat/43)
**Author:** [@zebrasecret](https://clash-lang.discourse.group/u/zebrasecret)\ **Replies:** 2\ **Last updated:** [September 25, 2024, 11:25pm UTC](https://clash-lang.discourse.group/t/unexpected-behavior-with-clog-and-snat/43 "2024-09-25T23:25:34Z")
I ran into an odd problem while writing a simple counter in clash - what I’m trying to do is specify the starting point for a “count down” timer using SNat: countDown'' :: forall n dom. (HiddenClockResetEnable dom) … --- ## [AutoReg - Uses beyond Maybe](https://clash-lang.discourse.group/t/autoreg-uses-beyond-maybe/42)
**Author:** [@Axman6](https://clash-lang.discourse.group/u/Axman6)\ **Replies:** 1\ **Last updated:** [August 8, 2024, 7:06am UTC](https://clash-lang.discourse.group/t/autoreg-uses-beyond-maybe/42 "2024-08-08T07:06:55Z")
I’ve got two AutoReg questions: Is there a reason there’s no instance for RamOp, other than no one’s written it? (I have now…\*) And it seems beneficial for there to be a version of mealy which uses AutoReg internally,… --- ## [How to write to a blockRam?](https://clash-lang.discourse.group/t/how-to-write-to-a-blockram/33)
**Author:** [@Ltbbb](https://clash-lang.discourse.group/u/Ltbbb)\ **Replies:** 6\ **Last updated:** [July 2, 2024, 12:12pm UTC](https://clash-lang.discourse.group/t/how-to-write-to-a-blockram/33 "2024-07-02T12:12:11Z")
As of right now I have a readOnly blockRam that stores a matrix of all 0s and the simulation works, but I would like to also be able to write to it. I know I should probably replace (pure Nothing) by something, but I do … --- ## [Clash Language Server](https://clash-lang.discourse.group/t/clash-language-server/30)
**Author:** [@TornadoStorm](https://clash-lang.discourse.group/u/TornadoStorm)\ **Replies:** 8\ **Last updated:** [June 13, 2024, 3:58pm UTC](https://clash-lang.discourse.group/t/clash-language-server/30 "2024-06-13T15:58:30Z")
Hello, While working on an assignment I noticed the Haskell Language Sever for VS Code does not always compile when programming with certain Clash code. Is there a way to make my HLS fully clash-compatible, or is there … --- ## [Type variable dom0 is ambiguous when using DomainPeriod](https://clash-lang.discourse.group/t/type-variable-dom0-is-ambiguous-when-using-domainperiod/28)
**Author:** [@jvnknvlgl](https://clash-lang.discourse.group/u/jvnknvlgl)\ **Replies:** 2\ **Last updated:** [June 12, 2024, 8:46am UTC](https://clash-lang.discourse.group/t/type-variable-dom0-is-ambiguous-when-using-domainperiod/28 "2024-06-12T08:46:08Z")
I’m using DomainPeriod to create a type based on Index that holds a maximum value for a 1.6 ms timer like this: type Timeout dom = Index (DivRU (1600000000) (Max 1 (DomainPeriod dom))) However, when I now try to use th… --- ## [Integrating Clash kernels with Vitis](https://clash-lang.discourse.group/t/integrating-clash-kernels-with-vitis/27)
**Author:** [@JasmijnB](https://clash-lang.discourse.group/u/JasmijnB)\ **Replies:** 1\ **Last updated:** [June 10, 2024, 7:33am UTC](https://clash-lang.discourse.group/t/integrating-clash-kernels-with-vitis/27 "2024-06-10T07:33:31Z")
I’d thought it’d be interesting to run Clash code on one of AMD’s accelerator cards by linking and managing the kernel using Vitis. For this I need an AXI-4 lite slave interface for control of the kernel and AXI4 m/stre… --- ## [Verilog and Vivado: 'x' (unknown logic value) is not supported by IP Packager](https://clash-lang.discourse.group/t/verilog-and-vivado-x-unknown-logic-value-is-not-supported-by-ip-packager/25)
**Author:** [@jvnknvlgl](https://clash-lang.discourse.group/u/jvnknvlgl)\ **Replies:** 1\ **Last updated:** [June 4, 2024, 11:40am UTC](https://clash-lang.discourse.group/t/verilog-and-vivado-x-unknown-logic-value-is-not-supported-by-ip-packager/25 "2024-06-04T11:40:51Z")
When I convert my Clash design to Verilog and then try to add it to a block design in Vivado, I get the following error: ‘x’ (unknown logic value) is not supported by IP Packager". Is there any way to fix this? --- ## [Converting \`Vec\` to \`BitVector\`](https://clash-lang.discourse.group/t/converting-vec-to-bitvector/23)
**Author:** [@Aleksander](https://clash-lang.discourse.group/u/Aleksander)\ **Replies:** 2\ **Last updated:** [May 6, 2024, 8:14pm UTC](https://clash-lang.discourse.group/t/converting-vec-to-bitvector/23 "2024-05-06T20:14:41Z")
How can I convert Vec bytes Byte to BitVector (bytes \* 8)? Is there a function similar to v2bv? --- ## [Generate HDL from a file not part of a cabal library](https://clash-lang.discourse.group/t/generate-hdl-from-a-file-not-part-of-a-cabal-library/22)
**Author:** [@cuddlefishie](https://clash-lang.discourse.group/u/cuddlefishie)\ **Replies:** 2\ **Last updated:** [April 8, 2024, 3:24pm UTC](https://clash-lang.discourse.group/t/generate-hdl-from-a-file-not-part-of-a-cabal-library/22 "2024-04-08T15:24:13Z")
I am working on some library, I have an example that can run in simulation but should also be able to translate to HDL. My cabal setup is project/ app/ Example.hs HdlTest.hs src/ ... In the project.caba… --- ## [Using numeric bounds with \`Vec\` functions, going from \`1 \<= n =\> Vec n a\` to \`Vec (m + 1) a\`](https://clash-lang.discourse.group/t/using-numeric-bounds-with-vec-functions-going-from-1-n-vec-n-a-to-vec-m-1-a/19)
**Author:** [@cuddlefishie](https://clash-lang.discourse.group/u/cuddlefishie)\ **Replies:** 2\ **Last updated:** [April 4, 2024, 3:37pm UTC](https://clash-lang.discourse.group/t/using-numeric-bounds-with-vec-functions-going-from-1-n-vec-n-a-to-vec-m-1-a/19 "2024-04-04T15:37:33Z")
I’m writing an interconnect that selects which subordinate to route a request to. For that I want to select which one to use based on an address. For that I have a vector that contains the (ascending) starting addresses… [Previous page](https://clash-lang.discourse.group/latest.md)